In general, a flat panel display, typified by a liquid crystal panel or an organic EL (electro-luminescence) panel, is constituted by a capacitive load. In a display control circuit for such application, an input digital video data signal is converted into an analog data signal and subjected to impedance conversion in an operational amplifier provided on the last stage of the control circuit.
As typical of this display control circuit, there is known such a circuit described for example in the Patent Document 1.
The display control circuit, described in the Patent Document 1, two operational amplifiers, namely an operational amplifier for discharge only, provided with a Pch input stage formed by Pch transistors, and an operational amplifier for charging only, provided with an Nch input stage formed by Nch transistors, are connected in parallel with an input.
In a driving method for a certain type of the liquid crystal panel, charging and discharge operations for a load are repeated alternately, that is, charging is first carried out and followed by discharging, followed in turn by charging, and so forth. In such case, no problem is raised even in the display control circuit described in the Patent Document 1.
However, such a driving method for a liquid crystal panel is sometimes used in which charging and discharge operations for a load are not necessarily repeated alternately, that is, charging and discharge operations for a load may be carried out at random, in such a manner that a charging operation, another charging operation, yet another charging operation, a discharge operation and another charging operation may be performed in this order. The display control circuit described in the Patent Document 1 is not up to such case.
There has also been proposed a display control circuit designed to perform a push-pull operation such that full-range input/output and charging/discharge for a load are possible with a sole operational amplifier. This display control circuit may be used unobjectionably for a driving method involving randomized charging/discharge operations such as one described above.
For such case, the operational amplifier comprises the combination of an input stage formed by P-channel transistors and an input stage formed by Nch transistors.
FIG. 10 is a diagram showing an illustrative structure of this type of the conventional display control circuit including a selector circuit 1 and an operational amplifier 2. The selector circuit 1 is connected to a digital image (or video) data signal line 100 to output an analog voltage corresponding to input digital image data. The operational amplifier 2 is connected to the output of the selector circuit 1 and is connected in a voltage-follower configuration, i.e., the operational amplifier 2 has a non-inverting terminal (+1) connected to the output of the selector circuit 10 and has an output terminal connected to an inverting-input terminal(−).
An illustrative structure of the operational amplifier, shown in FIG. 11, includes Nch transistors M1 and M2, forming a differential transistor pair, having sources connected common and having gates connected to input terminals 11 and 12, respectively, Pch transistors M3 and M4, forming a differential transistor pair, having sources connected common and having gates connected to input terminals 12 and 11, respectively, a first constant current source I1, connected across the sources of the Nch transistors M1 and M2, connected common, and a low potential side power supply terminal 14, a second constant current source I2, connected across the sources of the Pch transistors M3 and M4 and a high potential side power supply terminal 13, a first load circuit L1 connected across the drains of the Nch transistors M1 and M2 and the high potential side power supply terminal 13, a second load circuit L2 connected across the drains of the Pch transistors M3 and M4 and the low potential side power supply terminal 14, a Pch transistor M11 and an Nch transistor M12, forming an output stage circuit, and a driving stage circuit D1. The Pch transistor M11 and the Nch transistor M12 have sources connected to the high potential side power supply terminal 13 and to the low potential side power supply terminal 14, respectively, while having drains connected common to an output terminal 50. The driving stage circuit D1 level-shifts a signal 15, corresponding to outputs of the load circuits L1 and L2, rendered parallel, to send the resulting level-shifted signal to the gates of the Pch transistor M11 and the Nch transistor M12.
The operational amplifier, shown in FIG. 11, is connected in the voltage follower configuration, as shown in FIG. 10, such that one of the input terminals 12 is connected to the output terminal 50.
Referring to FIG. 11, the operation of this conventional operational amplifier is explained.
In the operational amplifier, shown in FIG. 11, the Nch transistors M1 and M2, and the Pch transistors M3 and M4, forming differential transistor pairs of the opposite conductivity types, are connected together to the input terminals 11 and 12, and respective outputs are taken out parallel as the signal 15, thus forming an input stage allowing for a full range input by complementary operation.
In the driving stage circuit D1, the signal 15 is level-shifted, and supplied to the gates of the Pch transistor M11 and the Nch transistor M12 of the output stage, such that, when a rising (charging) signal is supplied to the input stage, the driving stage circuit D1 receives a signal from the input stage to send such signals to the gates of the Pch transistor M11 and the Nch transistor M12 of the output stage by which the Pch transistor M11 and the Nch transistor M12 electrically charge a load, not shown, from the output terminal 50. The operation is reversed when a decaying (discharging) signal is supplied to the input stage.
In this manner, the Pch transistor M11 and the Nch transistor M12 of the output stage perform the push-pull operation to enable a wide range output to be produced.
That is, with the operational amplifier, shown in FIG. 11, the Pch input stage and the Nch input stage, comprising differential transistor pairs of respective opposite conductivity types, are tied to permit a full range input complementarily and a wide range output.
Other examples of the operational amplifier, in which two differential pair transistors of opposite conductivity types are tied and connected to the input terminals to permit a full-range input by complementary operation, are shown in for example the Patent Documents 2 and 3.
Referring to FIG. 12, the operational amplifier of the Patent Document 2 includes Nch transistors M1 and M2, forming a differential transistor pair, having sources connected common and having gates connected to input terminals 11 and 12, respectively, Pch transistors M3 and M4, forming a differential transistor pair, having sources connected common and having gates connected to input terminals 12 and 11, respectively, a first constant current source I1, connected across the sources of the Nch transistors M1 and M2, connected common, and a low potential side power supply terminal 14, and a second constant current source I2, connected across the sources of the Pch transistors M3 and M4, connected common, and a high potential side power supply terminal 13. The operational amplifier of the Patent Document 2 also includes a first current mirror circuit, made up by a Pch transistor M5 having a gate and a drain connected to a drain of the Nch transistor M1 and having a source connected to a high potential side power supply terminal 13, and a Pch transistor M6, having a gate connected to the gate of the Pch transistor M5, a drain connected to the drain of the Pch transistor M3 and a source connected to the high potential side power supply terminal 13, and a second current mirror circuit, made up by a Pch transistor M7, having a gate and a drain connected to a drain of the Nch transistor M2 and having a source connected to the high potential side power supply terminal 13, and a Pch transistor M8, having a gate connected to the gate of the Pch transistor M7, a drain connected to the drain of the Pch transistor M4 and a source connected to the high potential side power supply terminal 13. The operational amplifier of the Patent Document 2 also includes a load circuit, made up by Nch transistors M9 and M10, connected across the drains of the Pch transistors M3 and M4 and the low potential side power supply terminal 14, a Pch transistor M11 and an Nch transistor M12, forming an output stage circuit, each having a source connected to the high potential side power supply terminal 13 and to the low potential side power supply terminal 14 and having a drain connected common to an output terminal 50, and a driving circuit D1 for level-shifting a signal 16 from the drain of the Nch transistor M10 of the load circuit and for coupling the level-shifted signal to each of the gates of the Pch transistor M11 and the Nch transistor M12 of the output stage circuit.
The operational amplifier, shown in FIG. 12, is connected in the voltage-follower configuration, as shown in FIG. 10, so that the inverting input terminal 12 is connected to the output terminal 50.
Referring to FIG. 12, the operation of the conventional operational amplifier will be described.
Similarly to the operational amplifier, shown in FIG. 11, the operational amplifier, shown in FIG. 12, in which an Nch input stage and a Pch input stage of respective opposite conductivity types are tied together, permits a full-range input by complementary operation, while the output stage is designed to perform push-pull operations to yield a wide range output.
Moreover, the Nch transistor M1, forming a differential pair, has a drain connected in a current mirror configuration to a drain of the Pch transistor M3, forming the other differential pair, via a current mirror circuit, made up by Pch transistors M5 and M6, whilst the Nch transistor M2, forming the differential pair, has a drain connected in a current mirror configuration to a drain of the Pch transistor M4, forming the other differential pair, via another current mirror circuit, made up by Pch transistors M7 and M8. Thus, by momentarily increasing the bias current of the input stage only when a slew rate is needed, the charging or discharge speed may be increased without increasing the steady-state current.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-P2002-169501A
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-A-08-204470
[Patent Document 3]
JP Patent No. 3338771